During failure analysis of an integrated circuit (IC) chip, it is important to accurately identify the failing device or devices on the chip. Hence most FA tools provide marked areas that identify the potential failing devices in a dense layout of the chip, which is typically mounted in the FA tool for analysis. One conventional FA technique is the laser-assisted device alteration (LADA) technique, which creates time resolved images over a fixed field of view. These images have bright spots (hotspots) marking the potential problematic device locations. Users may view 100+ images at various time intervals. LADA technique works on all technology and will become increasingly important as FinFET's and conventional probing techniques phase out. The time resolved LADA technique scales with denser IC technology, while other probing techniques do not scale as well.
To overlay the set of images generated by the LADA technique with the layout, the user must align each image, or manually modify an image alignment file for the whole set of images, which is tedious. A need exists for a graphical user interface (GUI) to facilitate browsing through the images and to load the images in rapid succession (like a video). This will facilitate time based analysis of the potential failing devices.
FIG. 1 illustrates an embodiment of a failure analysis system 100 to conduct failure analysis on IC chips. The failure analysis system 100 comprises a user interface 102, a failure analysis tool 104, an IC chip 106, and a file system 108. The IC chip 106 is mounted in the failure analysis tool 104. The failure analysis tool 104 generates a set of images with hotspot markings indicating potential failing devices within the IC chip 106. The set of images is stored in the file system 108. The set of images may be displayed on the user interface 102 for failure analysis by an operator of the failure analysis system 100.